Conventional semiconductor integrated circuit packaging utilize flip chip ball grid array substrates form a grid array of pads on which solder balls are placed to provide the connections to the substrate. In the past, a substrate core was initially provided, followed by drilling, and conductive plating in layers to a conductive multilayer laminate. Typical FCBGA laminated substrates using this build up technology use a dielectric material such as glass clothe reinforced resin about 200-800 um in thickness for this middle core. Layers are built up on both sides of the middle core through a double sided process wherein corresponding layers are simultaneously formed on each side of the core to provide a laminate of layers. The middle core must include drilled holes plated with a metal, such as copper to provide paths for the electrical connection between the laminate layers on either side of the core. The core contributes desirable mechanical properties, such as high modulus and low CTE (coefficient of thermal expansion) that imparts handling strength and reduced warpage to the laminate. However, the drilled holes through the core, which must be relatively large, requires large areas in these micro-miniature structures. The core also imposes a significant thickness to the miniature structure. These aspects are less than desirable.
Accordingly, the FCBGA industries have been exploring and developing coreless FCBGA laminates. The advantage of such coreless laminates is that they do not have the limitations required for conducting wiring through the thick core, and thus, take advantage of the resulting higher wiring densities enabled at all levels of the coreless laminates. Consequently, cordless laminates having equivalent electrical function with fewer layers may be produced.
However, a trade-off or disadvantage of coreless laminates is the mechanical integrity or strength of a core structure. The coreless laminates are, at times, prone to high warpage and present handling challenges during both laminate fabrication and subsequent module assembly levels.
For example, a typical current process for fabricating coreless laminate structures begins with a stiff carrier, such as one made of conventional core material or heavy copper. A laminate is built up on each side of the carrier. Each laminate is intended to provide a separated coreless laminate chip support structure when the intermediate core is removed. However, such finished coreless laminate structures are difficult to handle as described above and are subject to warpage.